1. Field of the Invention
The present invention relates generally to the testing of digital circuits and more particularly to an apparatus for compaction of test stimuli and a method thereof.
2. Description of the Related Art
In order to ensure the production of reliable digital/computer systems, test stimuli are generated to test the systems. For a digital circuit, a test stimulus may be a single input pattern or a sequence of input patterns that comprises an initializing subsequence, a sensitizing subsequence and a propagation subsequence. In some cases the sensitizing subsequence is the same as the propagation subsequence. Hereafter the term “test vector” will also be used to represent a general test stimulus for a digital circuit and the term “test set” will be used to represent a set of test vectors.
An important objective of test generation is to achieve significant fault coverage with the generated test vectors for the circuit under test. The generation algorithms are such that, by of necessity concentrating on fault coverage, they generate sets of test vectors with redundancies. These redundancies are not easy to detect and result in a large set of test vectors.
The cost of applying the large set of test vectors is high since the cost of test equipment is related to its memory capacity. Thus, the number of test vectors impacts on the cost of testing which is indispensable in the production and maintenance of reliable digital/computer systems. Memory capacity is one of the main factors that determine the cost of test equipment. Large memory means high cost. If available test equipment does not have enough memory capacity for loading all the test vectors, then there is the need to load the test equipment more than once during test application to the circuit under test. More test vectors than can be contained in the memory of the test equipment calls for memory update (reloading of a subset of the test vectors) during test application. Re-loading of the test equipment during testing significantly prolongs the test application time (TAT). Even a single memory update leads to a big leap in the test application time. The long test application time impacts the time-to-market of the manufactured IC (integrated circuit) products.
It is evident, from the foregoing, that small test sets are desirable to reduce test cost and shorten the time-to-market of the reliable systems. Thus, there is the need to maintain a small number of test vectors. Reducing the number of the test vectors without compromising fault coverage is called test compaction. Test compaction algorithms should find ways of achieving small test sets without diminishing fault coverage. In other words, the algorithms should keep numbers of test vectors low while maintaining as high fault coverage as possible.
Two types of compaction techniques exist—dynamic and static compaction. Dynamic techniques attempt to reduce the number of test vectors while they are being generated. Often dynamic compaction requires the modification of the test generator. Static techniques, on the other hand, seek to reduce the number of the already generated test vectors. Thus static compaction is a post-processing step to test generation. Static techniques are therefore independent of the test generation algorithms and do not require any modifications of the algorithms. Moreover, even if dynamic compaction is used during test generation, static compaction can further reduce the size of the generated test set. This suggests that static compaction is more effective in reducing the sizes of test sets and hence the subsequent cost of testing.
Hsiao et al. have reported on their work on methods of test sequence compaction for sequential circuits in the following documents.    (1) M. S. Hsiao and S. T. Chakradhar, “Partitioning and reordering techniques for static test sequence compaction of sequential circuits,” Proc. of the 7th IEEE Asian Test Symposium, pp.452-457, 1998.    (2) M. S. Hsiao and S. T. Chakradhar, “State relaxation based subsequence removal for fast static compaction in sequential circuits,” Proc. of Design, Automation, and Test in Europe Conf., pp.577-582, 1998.    (3) M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Fast algorithms for static compaction of sequential circuit test vectors,” Proc. of IEEE VLSI Test Symposium, pp.188-195, 1997.
Their methods seek to shorten the sequences. Pomeranz et al. have proposed a method of efficient storage of test responses in the following document.    (4) I. Pomeranz and S. M. Reddy, “On test compaction objectives for combinational and sequential circuits,” Proc. of IEEE International Conference on VLSI Design, pp.279-284, 1998.
Kajihara et al. and Hamzaoglu et al., have reported on their work on test pattern compaction for combinational circuits in the following documents.    (5) S. Kajihara and K. Saluja, “On test pattern compaction using random pattern fault simulation,” Proc. Of IEEE International Conference on VLSI Design, pp.464-469, 1998.    (6) I. Hamzaoglu and J. H. Patel, “Test set compaction algorithms for combinational circuits,” Proc. of ACM International Conference on CAD, pp.283-289, 1997.
They have developed methods of static compaction that are tailor-made to work together with previously proposed methods of generating compact tests.
Digital systems employ both sequential and combinational circuits. Also, different test packages employ different test generation algorithms. Therefore, for a general digital circuit, there is the need for a general method of static test compaction the effectiveness of which is completely independent of any test generation algorithm.